Reductions in the size and inherent features of semiconductor devices (e.g., a metal-oxide semiconductor field-effect transistor) have enabled continued improvement in speed, performance, density, and cost per unit function of integrated circuits over the past few decades. In accordance with a design of the transistor and one of the inherent characteristics thereof, modulating the length of a channel region underlying a gate between a source and drain of the transistor alters a resistance associated with the channel region, thereby affecting the performance of the transistor. More specifically, shortening the length of the channel region reduces a source-to-drain resistance of the transistor, which, assuming other parameters are maintained relatively constant, may allow an increase in current flow between the source and drain when a sufficient voltage is applied to the gate of the transistor.
To further enhance the performance of MOS devices, stress may be introduced in the channel region of a MOS transistor to improve carrier mobility. Generally, it is desirable to induce a tensile stress in the channel region of an n-type metal-oxide-semiconductor (“NMOS”) device in a source-to-drain direction and to induce a compressive stress in the channel region of a p-type MOS (“PMOS”) device in a source-to-drain direction.
A commonly used method for applying compressive stress to the channel regions of PMOS devices is to grow SiGe stressors in the source and drain regions. Such a method typically includes the steps of forming a gate stack on a semiconductor substrate, forming spacers on sidewalls of the gate stack, forming recesses in the silicon substrate along the gate spacers, epitaxially growing SiGe stressors in the recesses, and then annealing. Since SiGe has a greater lattice constant than silicon has, it expands after annealing and applies a compressive stress to the channel region, which is located between a source SiGe stressor and a drain SiGe stressor. Similarly, stresses can be introduced to the channel regions of NMOS devices by forming SiC stressors. Since SiC has a smaller lattice constant than silicon has, it contracts after annealing and applies a tensile stress to the channel region.
The MOS devices formed from conventional stressor formation processes suffer leakage problems, however. To apply a greater stress to the channel region, the stressors need to have high germanium or carbon concentrations. High germanium or carbon concentrations in turn cause high defect concentrations, and thus cause an increase in junction leakage and a decrease in breakdown voltage. Accordingly, new methods for improving the stressor formation processes are needed.